SMSC LAN91C111 Manuale Utente Pagina 1

SMSC LAN91C111 REV C DATASHEET Revision 1.91 (08-18-08) DatasheetPRODUCT FEATURESLAN91C111 10/100 Non-PCI Ethernet Single Chip MAC + PHY  Single Chi

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 10 SMSC LAN91C111 REV CDATASHEETFigure 2.2 Pin Configuration - LAN91C11

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 100 SMSC LAN91C111 REV CDATASHEETHIGH-END ISA OR NON-BURST EISA MACHINE

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 101 Revision 1.91 (08-18-08)DATASHEETnIOWR nWR I/O Write strobe - asynchron

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 102 SMSC LAN91C111 REV CDATASHEETEISA 32 BIT SLAVE On EISA the LAN91C11

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 103 Revision 1.91 (08-18-08)DATASHEETLatched W-R combined with nCMD nRD I/

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 104 SMSC LAN91C111 REV CDATASHEETGND A1 Figure 12.3 LAN91C111 on EISA B

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 105 Revision 1.91 (08-18-08)DATASHEETChapter 13 Operational Description13.1

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 106 SMSC LAN91C111 REV CDATASHEETInput Leakage(All I and IS buffers exc

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 107 Revision 1.91 (08-18-08)DATASHEETCAPACITANCE TA = 25°C; fc = 1MHz; VCC

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 108 SMSC LAN91C111 REV CDATASHEET13.3 Twisted Pair Characteristics, Tra

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 109 Revision 1.91 (08-18-08)DATASHEET13.4 Twisted Pair Characteristics, Rec

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 11 Revision 1.91 (08-18-08)DATASHEETChapter 3 Block DiagramsThe diagram sho

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 110 SMSC LAN91C111 REV CDATASHEETChapter 14 Timing DiagramsFigure 14.1

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 111 Revision 1.91 (08-18-08)DATASHEETFigure 14.2 Asynchronous Cycle - Using

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 112 SMSC LAN91C111 REV CDATASHEETFigure 14.3 Asynchronous Cycle - nADS=

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 113 Revision 1.91 (08-18-08)DATASHEETPARAMETER MIN TYP MAX UNITSt26 ARDY Lo

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 114 SMSC LAN91C111 REV CDATASHEETFigure 14.6 Burst Read Cycles - nVLBUS

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 115 Revision 1.91 (08-18-08)DATASHEETFigure 14.7 Address Latching for All M

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 116 SMSC LAN91C111 REV CDATASHEETPARAMETER MIN TYP MAX UNITSt8 A1-A15,

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 117 Revision 1.91 (08-18-08)DATASHEETPARAMETER MIN TYP MAX UNITSt8 A1-A15,

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 118 SMSC LAN91C111 REV CDATASHEETAC TEST TIMING CONDITIONSUnless otherw

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 119 Revision 1.91 (08-18-08)DATASHEETTable 14.2 Receive Timing Characterist

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 12 SMSC LAN91C111 REV CDATASHEETThe diagram shown in Figure 3.2 describ

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 120 SMSC LAN91C111 REV CDATASHEETFigure 14.13 Collision Timing, Receive

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 121 Revision 1.91 (08-18-08)DATASHEETFigure 14.14 Collision Timing, Transmi

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 122 SMSC LAN91C111 REV CDATASHEETFigure 14.15 Jam Timingt41t40MII 100 M

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 123 Revision 1.91 (08-18-08)DATASHEETTable 14.4 Link Pulse Timing Character

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 124 SMSC LAN91C111 REV CDATASHEETFigure 14.16 Link Pulse TimingTPO±t42a

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 125 Revision 1.91 (08-18-08)DATASHEETFigure 14.17 FLP Link Pulse TimingTPO±

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 126 SMSC LAN91C111 REV CDATASHEETChapter 15 Package OutlinesNotes:1. Co

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 127 Revision 1.91 (08-18-08)DATASHEETNotes:1. Controlling Unit: millimeter2

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 128 SMSC LAN91C111 REV CDATASHEET Chapter 16 Revision HistoryTable 16.1

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 13 Revision 1.91 (08-18-08)DATASHEETFigure 3.3 LAN91C111 Physical Layer to

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 14 SMSC LAN91C111 REV CDATASHEETChapter 4 Signal DescriptionsTable 4.1

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 15 Revision 1.91 (08-18-08)DATASHEETChapter 5 Description of Pin FunctionsP

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 16 SMSC LAN91C111 REV CDATASHEET42 44 Local Bus Clock LCLK I** Input.

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 17 Revision 1.91 (08-18-08)DATASHEET9 11 EEPROM Clock EESK O4 Output. 4 μs

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 18 SMSC LAN91C111 REV CDATASHEETNote 5.1 If the EEPROM is enabled.125 1

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 19 Revision 1.91 (08-18-08)DATASHEETChapter 6 Signal Description Parameters

ORDER NUMBERS:LAN91C111-NC, LAN91C111i-NC (INDUSTRIAL TEMPERATURE)FOR 128-PIN QFP PACKAGESLAN91C111-NS, LAN91C111i-NS (INDUSTRIAL TEMPERATURE)FOR 128-

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 20 SMSC LAN91C111 REV CDATASHEETChapter 7 Functional Description7.1 Clo

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 21 Revision 1.91 (08-18-08)DATASHEET7.4 BIU BlockThe Bus Interface Unit can

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 22 SMSC LAN91C111 REV CDATASHEETThe MAC and external PHY communicate vi

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 23 Revision 1.91 (08-18-08)DATASHEETFigure 7.1 MI Serial Port Frame Timing

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 24 SMSC LAN91C111 REV CDATASHEET7.5.4 MII Packet Data Communication wit

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 25 Revision 1.91 (08-18-08)DATASHEETedges. RXD0 carries the least significa

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 26 SMSC LAN91C111 REV CDATASHEETOn the transmit side for 100Mbps TX ope

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 27 Revision 1.91 (08-18-08)DATASHEET10Mbps operation is similar to the 100M

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 28 SMSC LAN91C111 REV CDATASHEET* These 5B codes are not used. For dec

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 29 Revision 1.91 (08-18-08)DATASHEET7.7.4 Clock and Data RecoveryClock Reco

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 3 Revision 1.91 (08-18-08)DATASHEETTable of ContentsChapter 1 General Descr

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 30 SMSC LAN91C111 REV CDATASHEETIf 25 consecutive descrambled idle patt

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 31 Revision 1.91 (08-18-08)DATASHEETFigure 7.4 TP Output Voltage Template -

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 32 SMSC LAN91C111 REV CDATASHEETTransmit Level AdjustThe transmit outpu

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 33 Revision 1.91 (08-18-08)DATASHEETSTP (150 Ohm) Cable ModeThe transmitter

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 34 SMSC LAN91C111 REV CDATASHEETTP Squelch - 100 MbpsThe squelch block

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 35 Revision 1.91 (08-18-08)DATASHEETEqualizer DisableThe adaptive equalizer

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 36 SMSC LAN91C111 REV CDATASHEETSSD) is signaled to the controller inte

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 37 Revision 1.91 (08-18-08)DATASHEET7.7.12 Link Integrity & AutoNegotia

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 38 SMSC LAN91C111 REV CDATASHEET100BASE-TX Link Integrity Algorithm -10

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 39 Revision 1.91 (08-18-08)DATASHEETThe AutoNegotiation algorithm is initia

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 4 SMSC LAN91C111 REV CDATASHEET8.4 Bank Select Register . . . . . . .

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 40 SMSC LAN91C111 REV CDATASHEETdevice halts all transmissions includin

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 41 Revision 1.91 (08-18-08)DATASHEETAutopolarity DisableThe autopolarity fe

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 42 SMSC LAN91C111 REV CDATASHEETR/LT bits are also interrupt bits if th

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 43 Revision 1.91 (08-18-08)DATASHEETChapter 8 MAC Data Structures and Regis

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 44 SMSC LAN91C111 REV CDATASHEETThe receive byte count always appears a

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 45 Revision 1.91 (08-18-08)DATASHEETBROADCAST - Receive frame was broadcast

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 46 SMSC LAN91C111 REV CDATASHEETRegardless of the functional descriptio

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 47 Revision 1.91 (08-18-08)DATASHEETBank 7 is a new register Bank to the SM

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 48 SMSC LAN91C111 REV CDATASHEETFORCOL - When set, the FORCOL bit will

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 49 Revision 1.91 (08-18-08)DATASHEETSQET - Signal Quality Error Test. This

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 5 Revision 1.91 (08-18-08)DATASHEETChapter 15 Package Outlines . . . . . .

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 50 SMSC LAN91C111 REV CDATASHEETABORT_ENB - Enables abort of receive wh

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 51 Revision 1.91 (08-18-08)DATASHEET8.9 Bank 0 - Memory Information Registe

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 52 SMSC LAN91C111 REV CDATASHEETRegister) and determine the duplex mode

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 53 Revision 1.91 (08-18-08)DATASHEETLS2A, LS1A, LS0A – LED select Signal En

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 54 SMSC LAN91C111 REV CDATASHEETReserved – Must be 0.8.11 Bank 1 - Conf

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 55 Revision 1.91 (08-18-08)DATASHEET8.12 Bank 1 - Base Address RegisterThis

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 56 SMSC LAN91C111 REV CDATASHEET8.14 Bank 1 - General Purpose RegisterT

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 57 Revision 1.91 (08-18-08)DATASHEET8.15 Bank 1 - Control RegisterRCV_BAD -

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 58 SMSC LAN91C111 REV CDATASHEET8.16 Bank 2 - MMU Command RegisterThis

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 59 Revision 1.91 (08-18-08)DATASHEETNote: When using the RESET TX FIFOS co

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 6 SMSC LAN91C111 REV CDATASHEETList of FiguresFigure 2.1 Pin Configurat

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 60 SMSC LAN91C111 REV CDATASHEETThis register is updated upon an ALLOCA

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 61 Revision 1.91 (08-18-08)DATASHEETTEMPTY - No transmit packets in complet

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 62 SMSC LAN91C111 REV CDATASHEET8.20 Bank 2 - Data RegisterDATA REGISTE

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 63 Revision 1.91 (08-18-08)DATASHEETThis register can be read and written a

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 64 SMSC LAN91C111 REV CDATASHEET LATCOL - Late Collision 16COL - 16 c

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 65 Revision 1.91 (08-18-08)DATASHEETFigure 8.2 Interrupt StructureTX FIFO E

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 66 SMSC LAN91C111 REV CDATASHEET8.22 Bank 3 - Multicast Table Registers

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 67 Revision 1.91 (08-18-08)DATASHEET8.23 Bank 3 - Management InterfaceMSK_C

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 68 SMSC LAN91C111 REV CDATASHEET8.25 Bank 3 - RCV RegisterRCV DISCRD -

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 69 Revision 1.91 (08-18-08)DATASHEETCYCLE NCSOUT LAN91C111 DATA BUSAEN=0A3=

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 7 Revision 1.91 (08-18-08)DATASHEETList of TablesTable 4.1 LAN91C111 Pin Re

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 70 SMSC LAN91C111 REV CDATASHEETChapter 9 PHY MII Registers Multiple Re

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 71 Revision 1.91 (08-18-08)DATASHEETPHY Register DescriptionD[15:0] ↓Reg

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 72 SMSC LAN91C111 REV CDATASHEETREGAD[4:0] Register AddressIf REGAD[4:0

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 73 Revision 1.91 (08-18-08)DATASHEETTable 9.2 MII Serial Port Register MAPR

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 74 SMSC LAN91C111 REV CDATASHEET9.1 Register 0. Control RegisterRST - R

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 75 Revision 1.91 (08-18-08)DATASHEETDPLX - Duplex modeWhen Auto Negotiation

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 76 SMSC LAN91C111 REV CDATASHEETREM_FLT- Remote Fault Detect‘1’ indicat

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 77 Revision 1.91 (08-18-08)DATASHEETNP - Next PageA ‘1’ indicates the PHY w

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 78 SMSC LAN91C111 REV CDATASHEET9.6 Register 16. Configuration 1- Struc

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 79 Revision 1.91 (08-18-08)DATASHEET9.7 Register 17. Configuration 2 - Stru

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 8 SMSC LAN91C111 REV CDATASHEETChapter 1 General DescriptionThe SMSC LA

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 80 SMSC LAN91C111 REV CDATASHEET9.8 Register 18. Status Output - Struct

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 81 Revision 1.91 (08-18-08)DATASHEET9.9 Register 19. Mask - Structure and

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 82 SMSC LAN91C111 REV CDATASHEET9.10 Register 20. Reserved - Structure

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 83 Revision 1.91 (08-18-08)DATASHEETReserved:Reserved for Factory Use Reser

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 84 SMSC LAN91C111 REV CDATASHEETChapter 10 Software Driver and Hardware

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 85 Revision 1.91 (08-18-08)DATASHEET10.2 Typical Flow of Events for Transmi

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 86 SMSC LAN91C111 REV CDATASHEET10.3 Typical Flow of Events for Transmi

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 87 Revision 1.91 (08-18-08)DATASHEET10.4 Typical Flow of Event For Receive7

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 88 SMSC LAN91C111 REV CDATASHEETFigure 10.1 Interrupt Service RoutineIS

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 89 Revision 1.91 (08-18-08)DATASHEETFigure 10.2 RX INTRRX INTRWrite Ad. Ptr

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 9 Revision 1.91 (08-18-08)DATASHEETChapter 2 Pin ConfigurationsFigure 2.1 P

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 90 SMSC LAN91C111 REV CDATASHEETFigure 10.3 TX INTRTX Interrupt With AU

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 91 Revision 1.91 (08-18-08)DATASHEETFigure 10.4 TXEMPTY INTR (Assumes Auto

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 92 SMSC LAN91C111 REV CDATASHEETMEMORY PARTITIONINGUnlike other control

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 93 Revision 1.91 (08-18-08)DATASHEETmulticast packets that might not be for

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 94 SMSC LAN91C111 REV CDATASHEETFigure 10.6 Interrupt Generation for Tr

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 95 Revision 1.91 (08-18-08)DATASHEETChapter 11 Board Setup InformationThe f

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 96 SMSC LAN91C111 REV CDATASHEETSTORE and RELOAD bits of CTR will readb

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 97 Revision 1.91 (08-18-08)DATASHEETFigure 11.1 64 X 16 Serial EEPROM MapCO

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetRevision 1.91 (08-18-08) 98 SMSC LAN91C111 REV CDATASHEETChapter 12 Application ConsiderationsTh

10/100 Non-PCI Ethernet Single Chip MAC + PHYDatasheetSMSC LAN91C111 REV C 99 Revision 1.91 (08-18-08)DATASHEETD0-D31 D0-D31 32 bit data bus. The bus